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ltc694-3.3/ltc695-3.3 1 69453fb typical application features description 3.3v microprocessor supervisory circuits the ltc ? 694-3.3/ltc695-3.3 provide complete 3.3v power supply monitoring and battery control functions. these include power-on reset, battery back-up, ram write pro- tection, power failure warning and watchdog timing. the devices are pin compatible upgrades of the ltc694/ltc695 that are optimized for 3.3v systems. operating power consumption has been reduced to 0.6mw (typical) and 3w maximum in battery back-up mode. microprocessor reset and memory write protection are provided when the supply falls below 2.9v. the reset output is guaranteed to remain logic low with v cc as low as 1v. the ltc694-3.3/ltc695-3.3 power the active rams with a charge pumped nmos power switch to achieve low dropout and low supply current. when primary power is lost, auxiliary power, connected to the battery input pin, powers the rams in standby through an efficient pmos switch. for an early warning of impending power failure, the ltc694-3.3/ltc695-3.3 provide an internal comparator with a user-defined threshold. an internal watchdog timer is also available, which forces the reset pins to active states when the watchdog input is not toggled prior to a preset timeout period. reset output voltage vs supply voltage applications n guaranteed reset assertion at v cc = 1v n pin compatible with ltc694/ltc695 for 3.3v systems n 200a typical supply current n fast (30ns typ) onboard gating of ram chip enable signals n so-8 and s16 packages n 2.90v precision voltage monitor n power ok/reset time delay: 200ms or adjustable n minimum external component count n 1a maximum standby current n voltage monitor for power-fail or low-battery warning n thermal limiting n performance specified over temperature n 3.3v low power systems n critical p power monitoring n intelligent instruments n battery-powered computers and controllers n automotive systems l , lt, ltc, ltm, linear technology and the linear logo are registered trademarks of linear technology corporation. all other trademarks are the property of their respective owners. 1f v in 5v 3.3v 100f 0.1f p power power to cmos ram p system 0.1f 2.4v 51k 18k 694/5-3.3 ta01 microprocessor reset, battery back-up, ram write protection, power warning and watchdog timing are all in a single chip for 3.3v microprocessor system ltc695-3.3 v batt pfi v out v cc gnd decoder output ram cs p reset p nmi i/o line ce in ce out reset pfo wdi 0.1f 100 gnd v in v out lt1129-3.3 out sense shdn + + supply voltage (v) 0 reset output voltage (v) 3 4 5 4 2 1 0 1 2 3 5 694/5-3.3 ta02
ltc694-3.3/ltc695-3.3 2 69453fb absolute maximum ratings terminal voltage v cc .......................................................... C0.3v to 6v v batt ...................................................... C0.3v to 6v all other inputs ..................... C0.3v to (v out + 0.3v) input current v cc ..................................................................100ma v batt .................................................................25ma gnd ...................................................................10ma (notes 1 and 2) 1 2 3 4 5 6 7 8 top view n package 16-lead pdip 9 16 15 14 13 12 11 10 v cc v out v batt gnd batt on osc in low line osc sel wdo ce in reset reset ce out wdi pfi pfo t jmax = 110c, ja = 130c/w top view sw package 16-lead plastic wide so 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 v batt v out v cc gnd batt on low line osc in osc sel reset reset wdo ce in ce out wdi pfo pfi t jmax = 110c, ja = 130c/w 1 2 3 4 5 6 7 8 top view v cc v out pfi gnd wdi v batt pfo reset n8 package 8-lead pdip t jmax = 110c, ja = 130c/w 1 2 3 4 5 6 7 8 top view v batt v cc v out pfo pfi gnd s8 package 8-lead plastic so wdi reset t jmax = 110c, ja = 180c/w pin configuration v out output current ................. short-circuit protected power dissipation ............................................. 500mw operating temperature range ltc694c-3.3/ltc695c-3.3 ...................... 0c to 70c ltc694i-3.3/ltc695i-3.3 ....................C40c to 85c storage temperature range .................. C65c to 150c lead temperature (soldering, 10 sec)................... 300c
ltc694-3.3/ltc695-3.3 3 69453fb order information lead free finish tape and reel part marking package description temperature range ltc695cn-3.3#pbf ltc695cn-3.3#trpbf ltc695cn-3.3 16-lead pdip 0c to 70c ltc695in-3.3#pbf ltc695in-3.3#trpbf ltc695in-3.3 16-lead pdip C40c to 85c ltc695csw-3.3#pbf ltc695csw-3.3#trpbf ltc695csw-3.3 16-lead plastic wide so 0c to 70c ltc695isw-3.3#pbf ltc695isw-3.3#trpbf ltc695isw-3.3 16-lead plastic wide so C40c to 85c ltc694cn8-3.3#pbf ltc694cn8-3.3#trpbf ltc694cn8-3.3 8-lead pdip 0c to 70c ltc694in8-3.3#pbf ltc694in8-3.3#trpbf ltc694in8-3.3 8-lead pdip C40c to 85c ltc694cs8-3.3#pbf ltc694cs8-3.3#trpbf 6943 8-lead plastic so 0c to 70c ltc694is8-3.3#pbf ltc694is8-3.3#trpbf 694i3 8-lead plastic so C40c to 85c consult ltc marketing for parts specified with wider operating temperature ranges. consult ltc marketing for information on non-standard lead based finish parts. consult ltc marketing for military grade parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ pins reset threshold (v) watchdog timer battery back-up power-fail warning ram write protect push-button reset conditional battery back-up ltc694-3.3 8 2.90 x x x ltc695-3.3 16 2.90 x x x x ltc690 8 4.65 x x x ltc691 16 4.65 x x x x ltc694 8 4.65 x x x ltc695 16 4.65 x x x x ltc699 8 4.65 x ltc1232 8 4.37/4.62 x x ltc1235 16 4.65 x x x x x x product selection guide
ltc694-3.3/ltc695-3.3 4 69453fb electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 3.3v, v batt = 2v, unless otherwise noted. parameter conditions min typ max units battery back-up switching operating voltage range v cc v batt l l 3.0 1.5 5.50 2.75 v v v out output voltage i out = 1ma l v cc C 0.1 v cc C 0.2 v cc C 0.01 v cc C 0.01 v v i out = 50ma l v cc C 0.8 v cc C 0.4 v v out in battery back-up mode i out = 250a, v cc < v batt l v batt C 0.1 v batt C 0.02 v supply current (exclude i out )i out 50a, v cc = 3.6v l 0.2 0.2 0.6 1.0 ma ma supply current in battery back-up mode v cc = 0v, v batt = 2v l 0.04 0.04 1 5 a a battery standby current (+ = discharge, C = charge) 3.6v > v cc > v batt + 0.2v l C0.02 C0.10 0.02 0.10 a a battery switchover threshold (v cc C v batt ) power-up power-down 70 50 mv mv battery switchover hysteresis 20 mv batt on output voltage (note 4) i sink = 800a l 0.3 v batt on output short-circuit current (note 4) batt on = v out , sink current batt on = 0v, source current l 0.5 25 125 ma a reset and watchdog timer reset voltage threshold l 2.8 2.9 3.0 v reset threshold hysteresis 40 mv reset active time osc sel high, v cc = 3v l 160 140 200 200 240 280 ms ms watchdog timeout period, internal oscillator long period, v cc = 3v l 1.2 1.0 1.6 1.6 2.0 2.25 sec sec short period, v cc = 3v l 80 70 100 100 120 140 ms ms watchdog timeout period, external clock (note 5) long period, v cc = 3v short period, v cc = 3v l l 4032 960 4097 1025 clock cycles reset active time psrr 4 ms/v watchdog timeout period psrr, internal osc short period long period 2 32 ms/v ms/v minimum wdi input pulse width v il = 0.4v, v ih = 3v l 200 ns reset output voltage at v cc = 1v i sink = 10a, v cc = 1v l 4 200 mv reset and low _ line output voltage (note 4) i sink = 400a, v cc = 2.8v i source = 0.1a, v cc = 3v l l 2.3 0.3 v v reset and wdo output voltage (note 4) i sink = 400a, v cc = 3v i source = 0.1a, v cc = 2.8v l l 2.3 0.3 v v reset, reset , wdo , low _ line output short-circuit current (note 4) output source current output sink current l 13 9 25 a ma wdi input threshold logic low logic high l l 2.3 0.4 v v wdi input current wdi = v out wdi = 0v l l C50 4 C8 50 a a
ltc694-3.3/ltc695-3.3 5 69453fb electrical characteristics the l denotes the specifications which apply over the full operating temperature range, otherwise specifications are at t a = 25c. v cc = 3.3v, v batt = 2v, unless otherwise noted. parameter conditions min typ max units power-fail detector pfi input threshold l 1.25 1.3 1.35 v pfi input threshold psrr 0.3 mv/v pfi input current l 0.01 25 na pfo output voltage (note 4) i sink = 800a i source = 0.1a l l 2.3 0.3 v v pfo short-circuit source current (note 4) pfi = high, pfo = 0v pfi = low, pfo = v out l 13 17 25 a a pfi comparator response time (falling) v in = C20mv, v od = 15mv 2 s pfi comparator response time (rising) (note 4) v in = 20mv, v od = 15mv with 10k pull-up 40 8 s s chip enable gating ce in threshold v il v ih 1.9 0.45 v v ce in pull-up current (note 6) 3a ce out output voltage i sink = 800a i source = 400a i source = 1a, v cc = 0v l l l v out C 0.50 v out C 0.05 0.3 v v v ce in propagation delay c l = 20pf l 30 50 ns ce out output short-circuit current output source current output sink current 15 20 ma ma oscillator osc in input current (note 6) 2 a osc sel input pull-up current (note 6) 5a osc in frequency range osc sel = 0v osc sel = 0v, c a = 47pf l 0 4 125 khz khz note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: all voltage values are with respect to gnd. note 3: for military temperature range parts, consult the factory. note 4: the output pins of batt on, low _ line , pfo , wdo , reset and reset have weak internal pull-ups of typically 3a. however, external pull- up resistors may be used when higher speed is required. note 5: the external clock feeding into the circuit passes through the oscillator before clocking the watchdog timer. variation in the timeout period is caused by phase errors which occur when the oscillator divides the external clock by 64. the resulting variation in the timeout period is 64 plus one clock of jitter. note 6: the input pins of ce in, osc in and osc sel have weak internal pull-ups which pull to the supply when the input pins are floating.
ltc694-3.3/ltc695-3.3 6 69453fb typical performance characteristics power-fail comparator response time power-fail comparator response time power-fail comparator response time with pull-up resistor reset active time vs temperature reset voltage threshold vs temperature reset output voltage vs supply voltage output voltage vs load current output voltage vs load current power failure input threshold vs temperature load current (ma) 0 output voltage (v) 3.30 3.25 3.20 3.15 3.10 3.05 3.00 40 694/5-3.3 g01 10 20 30 50 slope = 4.6 v cc = 3.3v v batt = 2.4v t a = 25 c load current (a) 0 output voltage (v) 400 694/5-3.3 g02 100 200 300 500 2.40 2.39 2.38 2.37 2.36 2.35 v cc = 0v v batt = 2.4v t a = 25 c slope = 90 temperature ( c) C50 pfi input threshold (v) 1.310 1.308 1.306 1.304 1.302 1.300 1.298 1.296 1.294 25 75 694/5-3.3 g03 C25 0 50 100 125 v cc = 3.3v time (s) 0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 4 694/5-3.3 g04 123 5 1.305v 1.285v 8 7 6 v cc = 3.3v t a = 25 c v pfi = 20mv step pfo output voltage (v) 9 + C v pfi 1.3v 30pf pfo time (s) 0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 4 694/5-3.3 g06 2 6 1.315v 1.295v 12 10 8 v pfi = 20mv step 18 16 14 pfo output voltage (v) v cc = 3.3v t a = 25 c + C v pfi 1.3v 30pf 10k 3.3v pfo time (s) 0 3.5 3.0 2.5 2.0 1.5 1.0 0.5 0 40 694/5-3.3 g05 20 60 1.315v 1.295v 120 100 80 v pfi = 20mv step 180 160 140 pfo output voltage (v) v cc = 3.3v t a = 25 c + C v pfi 1.3v 30pf pfo temperature ( c) C50 reset active time (ms) 25 75 694/5-3.3 g07 C25 0 50 100 125 220 210 200 190 180 170 160 150 v cc = 3.3v temperature ( c) C50 reset voltage threshold (v) 2.90 2.89 2.88 2.87 2.86 2.85 2.84 25 75 694/5-3.3 g08 C25 0 50 100 125 v cc = 3.3v supply voltage (v) 0 reset output voltage (v) 3 4 5 4 2 1 0 1 2 3 5 694/5-3.3 g09
ltc694-3.3/ltc695-3.3 7 69453fb pin functions batt on: battery on logic output from comparator c2. batt on goes low when v out is internally connected to v cc . the output typically sinks 25ma and can provide base drive for an external pnp transistor to increase the output current above the 50ma rating of v out . batt on goes high when v out is internally switched to v batt . ce in: logic input to the chip _ enable gating circuit. ce in can be derived from microprocessors address line and/or decoder output. see the applications information section and figure 5 for additional information. ce out: logic output on the chip _ enable gating circuit. when v cc is above the reset voltage threshold, ce out is a buffered replica of ce in. when v cc is below the reset voltage threshold ce out is forced high (see figure 5). gnd: ground pin. low _ line : logic output from comparator c1. low _ line indicates a low line condition at the v cc input. when v cc falls below the reset voltage threshold (2.90v typically), low _ line goes low. as soon as v cc rises above the reset voltage threshold, low _ line returns high (see figure 1). low _ line goes low when v cc drops below v batt (see table 1). osc in: oscillator input. osc in can be driven by an external clock signal or an external capacitor can be con- nected between osc in and gnd when osc sel is forced low. in this configuration the nominal reset active time and watchdog timeout period are determined by the number of clocks or set by the formula (see the applications in- formation section). when osc sel is high or floating, the internal oscillator is enabled and the reset active time is fixed at 200ms typical for the ltc695-3.3. osc in selects between the 1.6 seconds and 100ms typical watchdog timeout periods. in both cases, the timeout period im- mediately after a reset is 1.6 seconds typical. osc sel: oscillator selection input. when osc sel is high or floating, the internal oscillator sets the reset active time and watchdog timeout period. forcing osc sel low, allows osc in to be driven from an external clock signal or an external capacitor can be connected between osc in and gnd. pfi: power failure input. pfi is the noninverting input to the power-fail comparator, c3. the inverting input is internally connected to a 1.3v reference. the power failure output remains high when pfi is above 1.3v and goes low when pfi is below 1.3v. connect pfi to gnd or v out when c3 is not used. pfo : power failure output from c3. pfo remains high when pfi is above 1.3v and goes low when pfi is below 1.3v. when v cc is lower than v batt , c3 is shut down and pfo is forced low. reset: active high logic output. it is the inverse of reset . reset : logic output for p reset control. whenever v cc falls below either the reset voltage threshold (2.90v, typi- cally) or v batt , reset goes active low. after v cc returns to 3.3v, the reset pulse generator forces reset to remain active low for a minimum of 140ms. when the watchdog timer is enabled but not serviced prior to a preset timeout period, the reset pulse generator also forces reset to ac- tive low for a minimum of 140ms for every preset timeout period (see figure 11). the reset active time is adjustable on the ltc695-3.3. an external push-button reset can be used in connection with the reset output. see push-but- ton reset in the applications information section. v batt : back-up battery input. when v cc falls below v batt , auxiliary power connected to v batt , is delivered to v out through pmos switch, m2. if back-up battery or auxiliary power is not used, v batt should be connected to gnd. v cc : 3.3v supply input. the v cc pin should be bypassed with a 0.1f capacitor. v out : voltage output for backed up memory. bypass with a capacitor of 0.1f or greater. during normal operation, v out obtains power from v cc through an nmos power switch, m1, which can deliver up to 50ma and has a typical on resistance of 5. when v cc is lower than v batt , v out is internally switched to v batt . if v out and v batt are not used, connect v out to v cc .
ltc694-3.3/ltc695-3.3 8 69453fb pin functions wdi: watchdog input. wdi is a three-level input. driving wdi either high or low for longer than the watchdog timeout period, forces both reset and wdo low. floating wdi disables the watchdog timer. the timer resets itself with each transition of the watchdog input (see figure 11). charge pump m2 m1 v batt v cc ce in pfi osc in osc sel wdi reset pulse generator watchdog timer reset batt on v out c1 1.3v gnd C + C + c2 osc transition detector C + c3 wdo reset pfo low line ce out 694/5-3.3 bd block diagram wdo : watchdog logic output. when the watchdog input remains either high or low for longer than the watchdog timeout period, wdo goes low. wdo is set high whenever there is a transition on the wdi pin, or low _ line goes low. the watchdog timer can be disabled by floating wdi (see figure 11).
ltc694-3.3/ltc695-3.3 9 69453fb applications information microprocessor reset the ltc694-3.3/ltc695-3.3 use a bandgap voltage refer- ence and a precision voltage comparator c1 to monitor the 3.3v supply input on v cc (see the block diagram). when v cc falls below the reset voltage threshold, the reset out- put is forced to active low state. the reset voltage threshold accounts for a 10% variation on v cc , so the reset output becomes active low when v cc falls below 3.0v (2.9v typi- cal). on power-up, the reset signal is held active low for a minimum of 140ms after reset voltage threshold is reached to allow the power supply and microprocessor to stabilize. the reset active time is adjustable on the ltc695-3.3. on power-down, the reset signal remains active low even with v cc as low as 1v. this capability helps hold the microprocessor in stable shutdown condition. figure 1 shows the timing diagram of the reset signal. the precision voltage comparator, c1, typically has 40mv of hysteresis which ensures that glitches at v cc pin do not activate the reset output. response time is typically 10ms. to help prevent mistriggering due to transient loads, the v cc pin should be bypassed with a 0.1f capacitor with the leads trimmed as short as possible. the ltc695-3.3 has two additional outputs: reset and low _ line . reset is an active high output and is the inverse of reset . low _ line is the output of the precision voltage comparator c1. when v cc falls below the reset voltage threshold, low _ line goes low. low _ line returns high as soon as v cc rises above the reset voltage threshold. battery switchover the battery switchover circuit compares v cc to the v batt input, and connects v out to whichever is higher. when v cc rises to 70mv above v batt , the battery switchover comparator, c2, connects v out to v cc through a charge pumped nmos power switch, m1. when v cc falls to 50mv above v batt , c2 connects v out to v batt through a pmos switch, m2. c2 has typically 20mv of hysteresis to prevent spurious switching when v cc remains nearly equal to v batt . the response time of c2 is approximately 20s. during normal operation, the ltc694-3.3/ltc695-3.3 use a charge-pumped nmos power switch to achieve low dropout and low supply current. this power switch can deliver up to 50ma to v out from v cc and has a typical on resistance of 5. the v out pin should be bypassed with a capacitor of 0.1f or greater to ensure stability. use of a larger bypass capacitor is advantageous for supplying current to heavy transient loads. when operating currents larger than 50ma are required from v out , or a lower dropout (v cc C v out voltage dif- ferential) is desired, the ltc695-3.3 should be used. this product provides batt on output to drive the base of an external pnp transistor (figure 2). if higher currents are needed with the ltc694-3.3, a high current schottky diode can be connected from the v cc pin to the v out pin to supply the extra current. v cc t 1 t 1 = reset active time v1 = reset voltage threshold v2 = reset voltage threshold + reset threshold hysteresis t 1 v2 v2 v1 v1 694/5-3.3 f01 reset low line figure 1. reset active time
ltc694-3.3/ltc695-3.3 10 69453fb applications information the ltc694-3.3/ltc695-3.3 are protected for safe area operation with short-circuit limit. output current is limited to approximately 200ma. if the device is overloaded for a long period of time, thermal shutdown turns the power switch off until the device cools down. the threshold temperature for thermal shutdown is approximately 155c with about 10c of hysteresis which prevents the device from oscillating in and out of shutdown. the pnp switch used in competitive devices was not chosen for the internal power switch because it injects unwanted current into the substrate. this current is collected by the v batt pin in competitive devices and adds to the charging current of the battery which can damage lithium batteries. the ltc694-3.3/ltc695-3.3 use a charge-pumped nmos power switch to eliminate unwanted charging current while achieving low dropout and low supply current. since no current goes to the substrate, the current collected by v batt pin is strictly junction leakage. a 125 pmos switch connects the v batt input to v out in battery back-up mode. the switch is designed for very low dropout voltage (input-to-output differential). this feature is advantageous for low current applications such as battery back-up in cmos ram and other low power cmos circuitry. the supply current in battery back-up mode is 1a maximum. the operating voltage at the v batt pin ranges from 1.5v to 2.75v. the charging resistor for rechargeable batteries should be connected to v out since this eliminates the discharge path that exists when the resistor is connected to v cc (figure 3). replacing the back-up battery when changing the back-up battery with system power on, spurious resets can occur while the battery is removed due to battery standby current. although battery standby current is only a tiny leakage current, it can still charge up the stray capacitance on the v batt pin. the oscillation cycle is as follows: when v batt reaches within 50mv of v cc , the ltc694-3.3/ltc695-3.3 switch to battery backup. v out pulls v batt low and the device goes back to normal operation. the leakage current then charges up the v batt pin again and the cycle repeats. if spurious resets during battery replacement pose no problems, then no action is required. otherwise, a resistor from v batt to gnd will hold the pin low while changing the battery. for example, the battery standby current is 1a maximum over temperature so the external resistor required to hold v batt below v cc is: r v cc ? 50mv 1a with v cc = 3v, a 2.7m resistor will work. with a 2v battery, this resistor will draw only 0.7a from the battery, which is negligible in most cases. figure 2. using batt on to drive external pnp transistor 3.3v 2.4v 0.1f 0.1f v batt v cc ltc695-3.3 v out gnd 4 3 1 2 5 any pnp power transistor 694/5-3.3 f02 batt on figure 3. charging external battery through v out 3.3v 2.4v 0.1f 0.1f v batt v cc ltc694-3.3 ltc695-3.3 v out gnd 694/5-3.3 f03 v out C v batt r i = r
ltc694-3.3/ltc695-3.3 11 69453fb applications information if battery connections are made through long wires, a 10 to 100 series resistor and a 0.1f capacitor are recommended to prevent any overshoot beyond v cc due to the lead inductance (figure 4). table 1 shows the state of each pin during battery back-up. when the battery switchover section is not used, connect v batt to gnd and v out to v cc . table 1. input and output status in battery back-up mode signal status v cc c2 monitors v cc for active switchover. v out v out is connected to v batt through an internal pmos switch. v batt the supply current is 1a maximum. batt on logic high. the open-circuit output voltage is equal to v out . pfi power failure input is ignored. pfo logic low. reset logic low. reset logic high. the open-circuit output voltage is equal to v out . low _ line logic low. wdi watchdog input is ignored. wdo logic high. the open-circuit output voltage is equal to v out . ce in chip _ enable input is ignored. ce out logic high. the open-circuit output voltage is equal to v out . osc in osc in is ignored. osc sel osc sel is ignored. memory protection the ltc695-3.3 includes memory protection circuitry which ensures the integrity of the data in memory by pre- venting write operations when v cc is at invalid level. two additional pins, ce in and ce out, control the chip _ enable or write inputs of cmos ram. when v cc is 3.3v, ce out follows ce in with a typical propagation delay of 30ns. when v cc falls below the reset voltage threshold or v batt , ce out is forced high, independent of ce in. ce out is an alternative signal to drive the ce , cs, or write input of battery backed up cmos ram. ce out can also be used to drive the store or write input of an eeprom, earom or novram to achieve similar protection. figure 5 shows the timing diagram of ce in and ce out. figure 4. 10/0.1f combination eliminates inductive overshoot and prevents spurious resets during battery replacement. the 2.7m pulls the v batt pin to ground while the battery is removed, eliminating spurious resets 2.7m 0.1f v batt ltc694-3.3 ltc695-3.3 gnd 694/5-3.3 f04 10 v cc v1 ce in v out = v batt ce out v out = v batt v2 v1 = reset voltage threshold v2 = reset voltage threshold + reset threshold hysteresis 694/5-3.3 f05 figure 5. timing diagram for ce in and ce out
ltc694-3.3/ltc695-3.3 12 69453fb ce in can be derived from the microprocessors address decoder output. figure 6 shows a typical nonvolatile cmos ram application. memory protection can also be achieved with the ltc694- 3.3 by using reset as shown in figure 7. power-fail warning the ltc694-3.3/ltc695-3.3 generate a power failure out- put ( pfo ) for early warning of failure in the microprocessors power supply. this is accomplished by comparing the power failure input (pfi) with an internal 1.3v reference. pfo goes low when the voltage at the pfi pin is less than 1.3v. typically pfi is driven by an external voltage divider (r1 and r2 in figures 8 and 9) which senses either an unregulated dc input or a regulated 3.3v output. the voltage divider ratio can be chosen such that the voltage at the pfi pin falls below 1.3v several milliseconds before the 3.3v supply falls below the maximum reset voltage threshold 3.0v. pfo is normally used to interrupt the microprocessor to execute shutdown procedure between pfo and reset or reset. the power-fail comparator, c3, does not have hysteresis. hysteresis can be added however, by connecting a resistor between the pfo output and the noninverting pfi input pin as shown in figures 8 and 9. the upper and lower trip points in the comparator are established as follows: when pfo output is low, r3 sinks current from the sum- ming junction at the pfi pin. v h =1.3v 1+ r1 r2 + r1 r3 ? ? ? ? ? ? when pfo output is high, the series combination of r3 and r4 source current into the pfi summing junction. v l = 1.3v 1 + r1 r2 ? (3.3v 1.3v)r1 1.3v(r3 + r4) ? ? ? ? ? ? assuming r4 << r3, v hysteresis = 3.3v r1 r3 applications information figure 6. a typical nonvolatile cmos ram application 3.3v 2.4v 0.1f 10f v batt v cc ltc695-3.3 v out gnd 694/5-3.3 f06 v cc reset ce in ce out reset 0.1f to p from decoder cs 30ns propagation delay 62512 ram gnd + 3.3v 2.4v 0.1f 10f v batt v cc v out gnd 694/5-3.3 f07 v cc reset 0.1f cs 62128 ram cs1 cs2 gnd ltc694-3.3 + figure 7. write protect for ram with ltc694-3.3 100f 694/5-3.3 f08 v cc 0.1f 10f to p pfo gnd v in 5v r4 10k pfi ltc694-3.3 ltc695-3.3 r1 51k r2 16k r3 200k 3.3v v in v out lt1129-3.3 shdn out sense adj + + figure 8. monitoring unregulated dc supply with the ltc694-3.3/ltc695-3.3s power-fail comparator figure 9. monitoring regulated dc supply with the ltc694-3.3/ltc695-3.3s power-fail comparator 10f 694/5-3.3 f09 0.1f to p v in r 6.5v 10f r3 2.7m 3.3v r1 27k r2 16k r5 5k v cc gnd pfo pfi ltc694-3.3 ltc695-3.3 r4 10k v in v out lt1129-3.3 shdn out sense adj + +
ltc694-3.3/ltc695-3.3 13 69453fb applications information example 1: the circuit in figure 8 demonstrates the use of the power-fail comparator to monitor the unregulated power supply input. assuming the the rate of decay of the supply input v in is 100mv/ms and the total time to execute a shutdown procedure is 8ms. also the noise of v in is 200mv. with these assumptions in mind, we can reasonably set v l = 5v which is 1.6v greater than the sum of maximum reset voltage threshold and the dropout voltage of the lt1129-3.3 (3v + 0.4v) and v hysteresis = 850mv. v hysteresis = 3.3v r1 r3 = 850mv r3 3.88 r1 choose r3 = 200k and r1 = 51k. also select r4 = 10k which is much smaller than r3. 5v =1.3v 1 ? 51k r2 ? (3.3v ? 1.3v)51k 1.3v(210k) ? ? ? ? ? ? r2 = 15.8k, choose nearest 5% resistor 16k and recal- culate v l , v l = 1.3v 1 + 51k 16k ? (3.3v ? 1.3v)51k 1.3v(210k) ? ? ? ? ? ? = 4.96 v v h = 1.3v 1 + 51k 16 k + 51k 2 00k ? ? ? ? ? ? = 5.77 v (4.96v ? 3.4v) 100mv / ms = 15.6ms v hysteresis = 5.77v C 4.96v = 810mv the 15.6ms allows enough time to execute shutdown pro- cedure for microprocessor and 810mv of hysteresis would prevent pfo from going low due to the noise of v in . example 2: the circuit in figure 9 can be used to measure the regulated 3.3v supply to provide early warning of power failure. because of variations in the pfi threshold, this circuit requires adjustment to ensure the pfi compara- tor trips before the reset threshold is reached. adjust r5 such that the pfo output goes low when the v cc supply reaches the desired level (e.g., 3.1v). monitoring the status of the battery c3 can also monitor the status of the memory back-up battery (figure 10). if desired, the ce out can be used to apply a test load to the battery. since ce out is forced high in battery back-up mode, the test load will not be applied to the battery while it is in use, even if the microprocessor is not powered. 2.4v 3.3v 694/5-3.3 f10 r1 1m r l 20k r2 1.6m optional test load low-battery signal t0 p i/o pin i/o pin v cc v batt gnd pfi ltc695-3.3 ce in pfo ce out figure 10. back-up battery monitor with optional test load watchdog timer the ltc694-3.3/ltc695-3.3 provide a watchdog timer function to monitor the activity of the microprocessor. if the microprocessor does not toggle the watchdog input (wdi) within a selected timeout period, reset is forced to active low for a minimum of 140ms. the reset active time is adjustable on the ltc695-3.3. since many systems can not service the watchdog timer immediately after a reset, the ltc695-3.3 has a longer timeout period (1.0 second minimum) right after a reset is issued. the normal timeout period (70ms minimum) becomes effective follow- ing the first transition of wdi after reset is inactive. the watchdog timeout period is fixed at 1.0 second minimum on the ltc694-3.3. figure 11 shows the timing diagram of watchdog timeout period and reset active time. the watchdog timeout period is restarted as soon as reset is inactive. when either a high-to-low or low-to-high transi- tion occurs at the wdi pin prior to timeout, the watchdog time is reset and begins to time out again. to ensure the watchdog time does not time out, either a high-to-low or low-to-high transition on the wdi pin must occur at or less than the minimum timeout period. if the input to the
ltc694-3.3/ltc695-3.3 14 69453fb wdi pin remains either high or low, reset pulses will be issued every 1.6 seconds typically. the watchdog time can be deactivated by floating the wdi pin. the timer is also disabled when v cc falls below the reset voltage threshold or v batt . the ltc695-3.3 provides an additional output (watchdog output, wdo ) which goes low if the watchdog timer is allowed to time out and remains low until set high by the next transition on the wdi pin. wdo is also set high when v cc falls below the reset voltage threshold or v batt . applications information the ltc695-3.3 has two additional pins, osc sel and osc in, which allow reset active time and watchdog timeout period to be adjusted per table 2. several configurations are shown in figure 12. osc in can be driven by an external clock signal or an external capacitor can be connected between osc in and gnd when osc sel is forced low. in these configura- tions, the nominal reset active time and watchdog timeout period are determined by the number of clocks or set by the formula in table 2. when osc sel is high or floating, t 1 = reset active time t 2 = normal watchdog timeout period t 3 = watchdog timeout period immediately after a reset v cc = 3.3v t 2 t 3 t 1 t 1 wdo wdi reset 694/5-3.3 f11 figure 11. watchdog timeout period and reset active time external clock internal oscillator 1.6 second watchdog internal oscillator 100ms watchdog external oscillator gnd gnd gnd gnd v cc v cc v cc osc sel osc sel osc sel osc sel osc in osc in osc in osc in 3 3 3 3 4 4 4 4 8 8 8 8 7 7 7 7 v cc floating or high floating or high ltc695-3.3 floating or high ltc695-3.3 ltc695-3.3 ltc695-3.3 694/5-3.3 f12 3.3v 3.3v 3.3v 3.3v figure 12. oscillator configurations
ltc694-3.3/ltc695-3.3 15 69453fb typical application capacitor back-up with 74hc4016 switch typical application r1 10k r2 30k 0.1f 0.1f 14 12 11 10 1 7 100f 13 2 3.3v v cc v out v batt 74hc4016 694/5-3.3 ta03 low line gnd ltc695-3.3 + table 2. ltc695-3.3 reset active time and watchdog timeout selections osc sel osc in watchdog timeout period reset active time normal (short period) immediately after reset (long period) ltc695-3.3 low external clock input 1024 clks 4096 clks 2048 clks low external capacitor* 400ms 70pf ?c 1.6s 70pf ?c 800ms 70pf ?c floating or high low 100ms 1.6 sec 200ms floating or high floating or high 1.6 sec 1.6 sec 200ms *the nominal internal frequency is 10.24khz. the nominal oscillator frequency with external capacitor is f osc (hz) = 184,000 c(pf) ? 1025 the internal oscillator is enabled and the reset active time is fixed at 140ms minimum for the ltc695-3.3. osc in selects between the 1 second and 70ms minimum normal watchdog timeout periods. in both cases, the timeout period immediately after a reset is at least 1 second. push-button reset the ltc694-3.3/ltc695-3.3 do not provide a logic input for direct connection to a push-button. however, a push- button in series with a 100 resistor connected to the reset output pin (figure 13) provides an alternative for manual reset. connecting a 0.1f capacitor to the reset pin debounces the push-button input. the 100 resistor in series with the push-button is re- quired to prevent the ringing, due to the capacitance and lead inductance, from pulling the reset pins of the mpu and ltc69x below ground. 3.3v 100 v cc ltc694-3.3 ltc695-3.3 gnd 694/5-3.3 f13 reset 0.1f mpu (e.g. 68hc05) reset figure 13. the external push-button reset
ltc694-3.3/ltc695-3.3 16 69453fb package description n8 package 8-lead pdip (narrow 0.300) (reference ltc dwg # 05-08-1510) .016 ? .050 (0.406 ? 1.270) .010 ? .020 (0.254 ? 0.508) 45 0 ? 8 typ .008 ? .010 (0.203 ? 0.254) so8 0303 .053 ? .069 (1.346 ? 1.752) .014 ? .019 (0.355 ? 0.483) typ .004 ? .010 (0.101 ? 0.254) .050 (1.270) bsc 1 2 3 4 .150 ? .157 (3.810 ? 3.988) note 3 8 7 6 5 .189 ? .197 (4.801 ? 5.004) note 3 .228 ? .244 (5.791 ? 6.197) .245 min .160 .005 recommended solder pad layout .045 .005 .050 bsc .030 .005 typ inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) n8 1002 .065 (1.651) typ .045 C .065 (1.143 C 1.651) .130 p .005 (3.302 p 0.127) .020 (0.508) min .018 p .003 (0.457 p 0.076) .120 (3.048) min 12 3 4 87 6 5 .255 p .015* (6.477 p 0.381) .400* (10.160) max .008 C .015 (0.203 C 0.381) .300 C .325 (7.620 C 8.255) .325 +.035 C.015 +0.889 C0.381 8.255 note: 1. dimensions are inches millimeters *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 inch (0.254mm) .100 (2.54) bsc s8 package 8-lead plastic small outline (narrow 0.150) (reference ltc dwg # 05-08-1610)
ltc694-3.3/ltc695-3.3 17 69453fb n16 1002 .255 .015* (6.477 0.381) .770* (19.558) max 16 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 .020 (0.508) min .120 (3.048) min .130 .005 (3.302 0.127) .065 (1.651) typ .045 ? .065 (1.143 ? 1.651) .018 .003 (0.457 0.076) .008 ? .015 (0.203 ? 0.381) .300 ? .325 (7.620 ? 8.255) .325 +.035 ?.015 +0.889 ?0.381 8.255 () note: 1. dimensions are inches millimeters *these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .010 inch (0.254mm) .100 (2.54) bsc n package 16-lead pdip (narrow 0.300) (reference ltc dwg # 05-08-1510) package description
ltc694-3.3/ltc695-3.3 18 69453fb s16 (wide) 0502 note 3 .398 ? .413 (10.109 ? 10.490) note 4 16 15 14 13 12 11 10 9 1 n 23 4 5 6 78 n/2 .394 ? .419 (10.007 ? 10.643) .037 ? .045 (0.940 ? 1.143) .004 ? .012 (0.102 ? 0.305) .093 ? .104 (2.362 ? 2.642) .050 (1.270) bsc .014 ? .019 (0.356 ? 0.482) typ 0 ? 8 typ note 3 .009 ? .013 (0.229 ? 0.330) .005 (0.127) rad min .016 ? .050 (0.406 ? 1.270) .291 ? .299 (7.391 ? 7.595) note 4 45 .010 ? .029 (0.254 ? 0.737) inches (millimeters) note: 1. dimensions in 2. drawing not to scale 3. pin 1 ident, notch on top and cavities on the bottom of packages are the manufacturing options. the part may be supplied with or without any of the options 4. these dimensions do not include mold flash or protrusions. mold flash or protrusions shall not exceed .006" (0.15mm) .420 min .325 .005 recommended solder pad layout .045 .005 n 1 2 3 n/2 .050 bsc .030 .005 typ sw package 16-lead plastic small outline (wide 0.300) (reference ltc dwg # 05-08-1620) package description
ltc694-3.3/ltc695-3.3 19 69453fb information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. revision history rev date description page number b 3/10 removed ul recognized and ul file number from the features section. 1 (revision history begins at rev b)
ltc694-3.3/ltc695-3.3 20 69453fb linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax: (408) 434-0507 www.linear.com ? linear technology corporation 2010 lt 0310 rev b ? printed in usa related parts typical application part number description comments ltc1326 micropower precision triple supply monitor 4.725v, 3.118v, 1v thresholds (0.75%) ltc1536 micropower triple supply monitor for pci applications meets pci t fail timing specifications write protect for additional rams 10f v batt v cc ltc695-3.3 v out gnd 694/5-3.3 ta04 v cc low line ce in ce out 0.1f cs 30ns propagation delay lh5168sh ram a 3.3v 2.4v 0.1f v cc lh5116s ram c v cc cs2 lh5116s ram b cs a cs b cs c cs1 cs1 optional connection for additional rams cs2 0.1f 0.1f +

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